`include "DDRStruct.vh"

module Axi_lite_DDR #(
    parameter integer C_S_AXI_DATA_WIDTH = 64,
    parameter integer C_S_AXI_ADDR_WIDTH = 64,
    parameter longint MEM_DEPTH          = 64'h80000000,
    parameter         FILE_PATH          = "testcase.hex"
) (
    AXI_ift.Slave  slave_ift,
    DDR_ift.Master ddr_request,

    output DDRStruct::DDRDebugCorePack ddr_debug_core
);

    Axi_lite_RAM #(
        .C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
        .C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
        .MEM_DEPTH         (MEM_DEPTH),
        .FILE_PATH         (FILE_PATH)
    ) axi_lite_ram (
        .slave_ift(slave_ift)
    );

    assign ddr_request.waddr_mem            = 64'b0;
    assign ddr_request.raddr_mem            = 64'b0;
    assign ddr_request.wdata_mem            = 128'b0;
    assign ddr_request.wen_mem              = 1'b0;
    assign ddr_request.ren_mem              = 1'b0;
    assign ddr_request.wmask_mem            = 16'b0;

    assign ddr_debug_core.debug_axi_rstate  = 2'b0;
    assign ddr_debug_core.debug_axi_wstate  = 2'b0;
    assign ddr_debug_core.debug_wen_mem     = 1'b0;
    assign ddr_debug_core.debug_ren_mem     = 1'b0;
    assign ddr_debug_core.debug_rvalid_mem  = 1'b0;
    assign ddr_debug_core.debug_wvalid_mem  = 1'b0;
    assign ddr_debug_core.debug_visit_times = 64'b0;

endmodule
